The good alternative was to use the AXI Data Mover. – The transfer commands are delivered by AXI4 Stream. – The status of transfers are delivered back by. The AXI Datamover is a key Interconnect Infrastructure IP which enables high throughput transfer of data between AXI4 memory mapped domain to AXI4- Stream. For you, you are probably looking at AXI Datamover or AXI Central DMA. ” Xilinx provides the AXI Virtual FIFO Controller core to use external.

Author: Akibei Gardat
Country: Australia
Language: English (Spanish)
Genre: Video
Published (Last): 12 September 2010
Pages: 397
PDF File Size: 18.67 Mb
ePub File Size: 9.20 Mb
ISBN: 850-1-16451-941-8
Downloads: 20654
Price: Free* [*Free Regsitration Required]
Uploader: Dajas

Your suggestions, indeed, solved the issue. I was just curious about your experience. All other trademarks are the property of their respective owners. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent.

Revision History The following table shows the revision history for this document. The VHDL code now does the following: I would really appreciate more insights getting the datamover to work has been really frustrating.

After that I just use a pointer to read out the contents of memory location 0x Still working on it though. Auto-suggest helps you quickly narrow down your search results by suggesting possible matches as you type. However, when a second write command is issued, the tready signal of the s2mm bus is deasserted, and never asserted again. I suspected that there might be something wrong with the command word I am sending but the logic analyzer data tells me otherwise from what I could tell.


Please upgrade to a Xilinx. Please upgrade to a Xilinx. But thanks to your sugestion, I tried once more with no result. For the mean time I have to settle with simulation to determine what is going on.

I am keeping a count of the 1us clock cycles to enable me to do that. As I am connecting a normal fifo to this input, which is not master axi, then I created an AXI fifo, with the correct width, validate, erase and finally with the correct width datamovee my normal fifo in the place I had it before. It’s the mechanism to propagate various parameters like data width. We share info about use of our site with social media, ads and analytics partners.

Sorry, you need to enable JavaScript to visit this website.

I’m sorry for the extra late reply, I was away from the lab for several weeks. It sounded like it would be sufficient for my purpose.

I greatly appreciate your help. Also, based on that, I have included a wait state that issues a command ahead of time after the data becomes available. Auto-suggest helps you quickly narrow down your search results by suggesting possible matches as you type. Embedded Processor System Design: By continuing to browse you are agreeing to use of cookies.

All forum topics Previous Topic Next Topic. We use cookies to personalise content and ads, to provide social media features and to analyse traffic. I am on a similar project but need a little bit more time to tell if it works as expected. Have you tried validating the block design? But if the datamover is connected to sHP or sGP ports, it will be bypassing cache.


AXI Datamover Design Problem – Community Forums

It is illegal for the core to deassert tvalid until tready accepts it. If it is then how would I know how many clock cycles are enough? The cmd state machine keeps on sending the same command word with every databeat. The bit value needs to be in a certain range and if it is not then I want to store the bit value in DDR S2MM along with the clock cycle it happened at.

AXI Datamover

Actually I do disable cache in my code before reading the memory location simply by including the following:. Could this still be the issue?

I would really appreciate some insight on what might I do to solve the problem. I have a state machine running for the datamovver that would send a bit data word every time a new value becomes available. ChromeFirefoxInternet Explorer 11Safari. I was not aware that the status interface had the ability to prevent data from being transferred.

See details or close this message. I am wondernig if datamver in the AXI bus in not sequencing correctly. I use the regular fifos as I need to cross clock domains and change the data width accordingly to mantain my throughput. I will need to do that for a maximum ofclock cycles ms.